Although this design delivers extremely high bandwidth, its packaging process is complex and costly, which is one of the key reasons why AI GPUs remain expensive today.

Intel aims to eliminate the silicon interposer altogether through XBM, thereby reducing the overall package size and lowering manufacturing costs.

Another major change is the interface design.

Traditional HBM relies on a 1024-bit or even wider parallel bus to deliver bandwidth, whereas XBM adopts UCIe (Universal Chiplet Interconnect Express), a 32 GT/s serial high-speed interconnect, with the Base Die handling the SerDes. Series-Parallel Conversion ).

In other words, XBM transforms the traditional HBM’s ultra-wide bus into high-speed serial communication, aligning the overall design more closely with the Chiplet‑era paradigm while reducing packaging and interconnect complexity.

The patent also proposes an even more radical design.

Traditional DRAM transistors are located in the front-end-of-line (FEOL) region of the wafer, whereas the XBM project aims to place… 1T1C DRAM cell placed on the BEOL (Back-End-Of-Line) metal interconnect layer. , adopt Thin-film transistor (Thin Film Transistor) implementation.

The advantages of this approach include the ability to partition memory into more independent data blocks, facilitate higher‑density stacking, and create room for further integration of logic and storage in the future.

This is also one of the “Backend Transistor” technology pathways that Intel has been exploring in recent years.

In the AI era, HBM typically requires stacking of eight or even sixteen layers. However, the higher the layer count, the lower the manufacturing yield. To address this, XBM incorporates extensive self‑repair features, including Built‑In Self‑Repair (BISR), spare memory channels, redundant memory arrays, and debugging and fault‑diagnosis logic.

This means that even if some memory cells are defective, spare areas can be used for replacement, thereby increasing the final yield and reducing manufacturing costs.

According to the patent description, a single-layer die has a capacity of approximately 1.5 GB and is initially configured with an 8‑layer stack, which can be expanded to 16 layers. Data is transmitted via TSVs and ultimately routed through the base die to the compute chip.

The overall package dimensions are intended to remain comparable to those of HBM4.

It is worth noting that XBM is not the same technology previously co-developed by Intel and SAIMEMORY, a subsidiary of SoftBank. ZAM (Z-Angle Memory) 。

The two routes are different:

The main innovation of ZAM lies in… Hybrid bonding (Hybrid Bonding) and stacking approaches aim to increase capacity and bandwidth while reducing power consumption, all while preserving the conventional DRAM architecture. The current target for commercialization is around 2029.

XBM, on the other hand, further modifies the DRAM cell architecture, packaging approach, and interface protocol, effectively resembling a completely new HBM‑alternative architecture.

This means that Intel is, in fact, simultaneously advancing multiple next-generation AI memory technology pathways.

If XBM can achieve mass production in the future, it could reduce HBM package costs and alleviate the current situation. CoWoS and the issue of tight capacity for silicon interposers; at the same time, it is driving the development of the UCIe ecosystem, making AI chips and memory more modular and adopting a chiplet-based architecture.

For industry users, this also helps alleviate the “memory wall” bottleneck in AI servers, further boosting the efficiency of large‑model training and inference. Notably, it will also exert sustained competitive pressure on the existing HBM supply chain, including vendors that rely on conventional HBM packaging solutions.

However, at present, XBM remains only at the stage of... Patent stage The patent was filed at the end of 2024 and made public this year. Intel has yet to disclose any product roadmap or commercialization timeline, leaving significant uncertainty about whether mass production will materialize in the future.